As the semiconductor integrated circuit development follows a schedule predicted by Moore's law, the device feature size becomes smaller and more integrated. With continuous miniaturization in the feature size, the single chip has achieved an integration level as high as 108˜109, and meanwhile, more and more requirements are posed on the production technique, thus reducing defect size and density becomes very crucial in the manufacture process. A 1 micron dust may not be a problem to a transistor of 100 micron in size, but it will be a fatal defect causing device failure to a transistor of 1 micron, hence much higher requirements are raised to the chemical vapor deposition (CVD) thin film recipe. Making 90 nm or 60 nm devices under the same thin film deposition process, the negative impact of 10 defects in same size on the yield of 90 nm products is less than 2% but on 65 nm products, is more than 30%.
In the current CVD recipe, defects caused by the high density plasma chemical vapor deposition (HDP CVD) recipe, such as HDP CVD recipe of shallow trench isolation (STI) dielectrics and HDP CVD recipe of phosphosilicate glass (PSG) as an interlayer dielectric (ILD) layer are most serious. In the current recipe, block defects will be produced if the HDP CVD process of PSG as an ILD is not well controlled, causing contact bridge in the following recipe, thus resulting in a product failure, referring to FIGS. 1-4 for details.
FIG. 1 shows a typical CMOS structure with an ILD. On substrate 10 an N well 11 and a P well 12 separated by an STI structure 13 are disposed. NMOS and PMOS have source/drain 22 and gate 21. An ILD 14 formed by an HDP CVD process covers the NMOS and PMOS enclosed by the strained SiN. A defect 15, such as a contaminant particle unpredictable in the process, exists in the ILD 14. When the ILD 14 is formed, the defect 15 is removed by washing and chemical mechanical polishing (CMP), but a hole 16 is left in the ILD 14, referring to FIG. 2. Then, referring to FIG. 3, through the ILD 14, multiple contact holes 17 are formed to expose electrodes out. Next, referring to FIG. 4, conductive materials such as Ti/TiN are filled to form contact plugs 19 in contact holes 17, but having some conductive materials left in holes 16 at the same time, thus a bridge unit 18 is formed. Due to storage of the bridge unit 18, multiple contact plugs 19 are bridged to be short-circuited, thereby resulting in a circuit failure.
Therefore, in accordance with the further requirement on the HDP CVD technical yield posed by the current semiconductor recipe, there is a need to develop a method for eliminating contact bridge in a contact hole process to reduce the defects produced in the HDP CVD deposition process, thereby avoiding a circuit failure.